// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  scd_reg_offset.h
// Project line  :  K3
// Department    :  K3
// Author        :  Huawei
// Version       :  V100
// Date          :  2015/4/10
// Description   :  HiVcodecV100 VDEC
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/04/10 10:02:43 Create file
// ******************************************************************************

#ifndef __SCD_REG_OFFSET_H__
#define __SCD_REG_OFFSET_H__

/* SCD Base address of Module's Register */
#define SOC_SCD_BASE                       (0xc800)

/******************************************************************************/
/*                      SOC SCD Registers' Definitions                            */
/******************************************************************************/

#define SOC_SCD_SCD_START_REG         (SOC_SCD_BASE + 0x0)  
#define SOC_SCD_LIST_ADDRESS_REG      (SOC_SCD_BASE + 0x4)  
#define SOC_SCD_UP_ADDRESS_REG        (SOC_SCD_BASE + 0x8)  
#define SOC_SCD_UP_LEN_REG            (SOC_SCD_BASE + 0xC)  
#define SOC_SCD_BUFFER_FIRST_REG      (SOC_SCD_BASE + 0x10) 
#define SOC_SCD_BUFFER_LAST_REG       (SOC_SCD_BASE + 0x14) 
#define SOC_SCD_BUFFER_INI_REG        (SOC_SCD_BASE + 0x18) 
#define SOC_SCD_SCD_INT_MASK_REG      (SOC_SCD_BASE + 0x1C) 
#define SOC_SCD_SCD_PROTOCOL_REG      (SOC_SCD_BASE + 0x20) 
#define SOC_SCD_SCD_NORM_INI_CLR_REG  (SOC_SCD_BASE + 0x24) 
#define SOC_SCD_SCD_PREVIOUS_LSB_REG  (SOC_SCD_BASE + 0x3C) 
#define SOC_SCD_SCD_INT_FLAG_REG      (SOC_SCD_BASE + 0x40) 
#define SOC_SCD_SCD_PREVIOUS_MSB_REG  (SOC_SCD_BASE + 0x44) 
#define SOC_SCD_SCD_BYTE_VALID_REG    (SOC_SCD_BASE + 0x48) 
#define SOC_SCD_SCD_NUMBER_REG        (SOC_SCD_BASE + 0x4C) 
#define SOC_SCD_RLL_ADDR_REG          (SOC_SCD_BASE + 0x50) 
#define SOC_SCD_SCR_RAT_REG           (SOC_SCD_BASE + 0x54) 
#define SOC_SCD_SCR_OFFSET_REG        (SOC_SCD_BASE + 0x58) 
#define SOC_SCD_SCR_NXT_ADDR_REG      (SOC_SCD_BASE + 0x5C) 
#define SOC_SCD_STA_REG               (SOC_SCD_BASE + 0x60) 
#define SOC_SCD_SDWR_REG              (SOC_SCD_BASE + 0x64) 
#define SOC_SCD_RUN_CYCLE_REG         (SOC_SCD_BASE + 0x68) 
#define SOC_SCD_SCD_RD_REQ_REG        (SOC_SCD_BASE + 0x6C) 
#define SOC_SCD_SCD_RD_DAT_REG        (SOC_SCD_BASE + 0x70) 
#define SOC_SCD_SCD_WR_REQ_REG        (SOC_SCD_BASE + 0x74) 
#define SOC_SCD_SCD_WR_DAT_REG        (SOC_SCD_BASE + 0x78) 
#define SOC_SCD_SCD_WORK_ST_REG       (SOC_SCD_BASE + 0x7C) 
#define SOC_SCD_SCD_CLK_CFG_REG       (SOC_SCD_BASE + 0x80) 
#define SOC_SCD_SCD_ARBIT_DG0_REG     (SOC_SCD_BASE + 0x84) 
#define SOC_SCD_SCD_ARBIT_DG1_REG     (SOC_SCD_BASE + 0x88) 
#define SOC_SCD_SCD_ARBIT_DG2_REG     (SOC_SCD_BASE + 0x8C) 
#define SOC_SCD_SCD_ARBIT_DG3_REG     (SOC_SCD_BASE + 0x90) 
#define SOC_SCD_SCD_SOFTRST_DG0_REG   (SOC_SCD_BASE + 0x94) 
#define SOC_SCD_SCD_SOFTRST_DG1_REG   (SOC_SCD_BASE + 0x98) 
#define SOC_SCD_SCD_SAFE_INT_MASK_REG (SOC_SCD_BASE + 0xC4) 
#define SOC_SCD_SCD_SAFE_INI_CLR_REG  (SOC_SCD_BASE + 0xC8) 

#endif // __SCD_REG_OFFSET_H__
